Semiconductor-metal-oxide (MOS) devices, also referred to as transistors, are core devices in the modem integrated circuits. MOS devices are typically formed in well regions, which are doped with p-type or n-type impurities. N-type MOS (NMOS) devices are typically formed in p-type well regions, while p-type MOS (PMOS) devices are typically formed in n-type well regions.
Well regions need to be formed prior to the formation of MOS devices. The formation processes of well regions involve the processes of forming and patterning masks and implanting desired impurities. FIG. 1 illustrates a cross-sectional view of a typical well formation process. Photoresist 6 is formed on substrate 2, through which a portion of semiconductor substrate 2 is exposed. An implantation, which is symbolized by arrows 8, is then performed to introduce impurities into substrate 2, and thus well region 4 is formed.
The conventional well implantation process suffers from well proximity effects. At the time the atoms of the implanted impurities are introduced into well region 4, the impurity atoms are also implanted into photoresist 6. Colliding with the atoms/molecules in photoresist 6, the impurity atoms will have increasingly smaller speeds as they travel in photoresist 6. The collision will also cause the scattering of impurity atoms, particularly the impurity atoms with reduced speeds. For the impurity atoms close to the edges of photoresist 6, there is a chance that they will be scattered out of photoresist 6 and re-implanted into well region 4, wherein the re-implanted atoms are schematically illustrated as arrows 10.
It can be found that the well proximity effects are layout related, which means that the severity of well proximity effects are affected by distance D between neighboring photoresist 6. With a smaller distance D, more impurity atoms are re-implanted per unit area. Conversely, with a greater distance D, less impurity atoms are re-implanted per unit area. The re-implanted atoms cause an increase in the impurity concentration in well region 4. The increased impurity concentration in a channel region 12 of a subsequently formed MOS device adversely affects threshold voltage and drive current.
The impurity re-implantation is affected by various factors, such as distance D, the energy of implanted impurity atoms, and the type of the impurity, etc. It is thus very difficult to model and to compensate for the well proximity effects. Therefore, a method for reducing the layout-related well proximity effects is needed.